Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a plurality of stacked semiconductor chips.
Packaging technology for integrated semiconductor devices has been continuously developed according to demands for the semiconductor device which is miniaturized and has a large capacity. Recently, a variety of technologies for stacked semiconductor packages capable of satisfying characteristics with respect with mounting efficiency as well as the miniaturization and large capacity have been developed.
The stacked semiconductor package may be fabricated by two methods. The first method is to stack individual semiconductor chips and package the stacked individual semiconductor chips at once. The second method is to stack individual semiconductor chips which are packaged. The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or through-silicon-vias (TSVs).
In the case of the conventional stacked semiconductor package using metallic wires, its operating speed is low because the electrical signal exchange is performed through the metallic wires, and electrical characteristics are degraded because a large number of wires are used. Furthermore, the size of the package may increase due to an additional area for forming the metallic wires in a substrate, and the height of the package may increase due to a gap for wire bonding between the semiconductor chips.
Recently, a stacked semiconductor package using a TSV has been developed. In general, the stacked semiconductor package is fabricated by the following method. First, a via hole passing through a semiconductor chip is formed in the semiconductor chip, and a through electrode called a TSV is formed by filling the via hole with a conductive material. Then, an upper semiconductor chip and a lower semiconductor chip are electrically coupled via the through electrode.